Wavebubble 2010 Hardware Test

pll.h

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00001 
00008 #ifndef PLL_H_
00009 #define PLL_H_
00010 
00011 #define pll_set_rf(x, n) pll_set_freq(x, n, 0x1);
00012 #define pll_set_if(x, n) pll_set_freq(x, n, 0x4);
00013 
00014 #define PLLCLK_DDR      DDRD    //!< PLL clock direction port
00015 #define PLLCLK_PORT     PORTD   //!< PLL clock output port
00016 #define PLLCLK          PD5     //!< PLL clock pin
00017 
00018 #define PLLDATA_DDR     DDRD    //!< PLL data direction port
00019 #define PLLDATA_PORT    PORTD   //!< PLL data output port
00020 #define PLLDATA         PD6     //!< PLL data pin
00021 
00022 #define PLLLE_DDR       DDRB    //!< PLL enable direction port
00023 #define PLLLE_PORT      PORTB   //!< PLL enable output port
00024 #define PLLLE           PB0     //!< PLL enable pin
00025 
00026 #define PLL_RFIN_DDR    DDRC    //!< PLL RF lock detect direction port
00027 #define PLL_IFIN_DDR    DDRC    //!< PLL IF lock detect direction port
00028 #define PLL_RFIN        PC0     //!< PLL RF lock detect pin
00029 #define PLL_IFIN        PC5     //!< PLL IF lock detect pin
00030 #define PLL_RFIN_PIN    PINC    //!< PLL RF input port
00031 #define PLL_IFIN_PIN    PINC    //!< PLL IF input port
00032 #define PLL_RFIN_PORT   PORTC   //!< PLL RF output port
00033 #define PLL_IFIN_PORT   PORTC   //!< PLL IF output port
00034 
00035 
00036 void pll_tx(uint32_t data, uint8_t addr) ;
00037 void pll_init(void) ;
00038 void pll_set_rcounter(uint16_t rcounter);
00039 void pll_set_freq(uint16_t rf_freq, uint8_t prescaler, uint8_t reg);
00040 uint8_t tune_rf(uint16_t freq);
00041 uint8_t tune_if(uint16_t freq);
00042 void pll_init(void);
00043 uint8_t tune_rf_band(uint16_t min, uint16_t max, uint8_t vco_num);
00044 
00045 #endif /* PLL_H_ */