Question about the USBtinyISP circuit as pictured here.
MISO is an input pin from the perspective of the ATtiny, so it obviously wouldn't work to send it through the '125 buffer in the same direction as MOSI, SCK, and RST. But what good does it do to send it through the buffer at all? The MISO pin's voltage going into the '125 is always going to be the same as the '125's output voltage, so it isn't providing level-translation functionality. It's just passing the signal through. I suspect it works because most target-voltage logic levels are going to be detectable by the ATtiny's MISO input.
I can think of three reasons: (1) buffers buffer, so a voltage spike would kill the inexpensive buffer and save the more expensive ATtiny; and (2) it prevents skew in the timing of the four SPI signals, though I can't imagine that that would make a difference at the sub-MHz speeds of this circuit. The third reason, which I don't really buy, is that it just looks better in the schematic. More symmetry, or something like that.
Does any of this resemble the truth?
USBtinyISP's buffer & MISO
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- sdb
- Posts: 31
- Joined: Thu Jan 12, 2012 4:24 am
Re: USBtinyISP's buffer & MISO
I wondered the same thing...
It isn't adding any additional components so I just figured #1 was good enough for me. Even if whomever added the buffer in was just thinking "add a buffer for the correct I/O voltage" without ever thinking any deeper about the implications, given the direction of that particular signal.
It isn't adding any additional components so I just figured #1 was good enough for me. Even if whomever added the buffer in was just thinking "add a buffer for the correct I/O voltage" without ever thinking any deeper about the implications, given the direction of that particular signal.
Please be positive and constructive with your questions and comments.