I was able to trak the cause of this down to the point where it waits for a read to be finished.
- Code: Select all
while(!(TWCR & (1<<TWINT)));
Does that ring a bell? Are there some known errors with this?
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while(!(TWCR & (1<<TWINT)));static unsigned char twi_op (unsigned char op)
{
TWCR = op;
while (! bit_tst (TWCR, TWINT)) ; // wait for TWINT
return TWSR & 0xF8;
} // twi_op
#define TWI_OP (1<<TWINT | 1<<TWEN)
static void ds1307_read_buf (unsigned char addr, unsigned char *buf, unsigned char n)
{
int j;
if (twi_op (TWI_OP | 1<<TWSTA) != 0x08) // START condition
goto bailout;
TWDR = DS1307_W; // WRITE command
if (twi_op (TWI_OP) != 0x18) goto bailout;
TWDR = addr; // DS1307 address
if (twi_op (TWI_OP) != 0x28) goto bailout;
if (twi_op (TWI_OP | 1<<TWSTA) != 0x10) // Repeated START
goto bailout;
TWDR = DS1307_R; // READ command
if (twi_op (TWI_OP) != 0x40) goto bailout;
for (j=0; j < n-1; j++) { // read all bytes except the last with following ACK
if (twi_op (TWI_OP | 1<<TWEA) != 0x50) goto bailout;
buf[j] = TWDR;
}
if (twi_op (TWI_OP) != 0x50) goto bailout; // read the last byte without ACK
buf[n-1] = TWDR;
bailout:
TWCR = TWI_OP | 1<<TWSTO;
} // ds1307_read_buf
(REGISTER & (1 << BIT_NUMBER))while(1) {
someADCstuff();
if((IRQ_0 & 0x1)){
IRQ_0 &= ~0x1;
readIOexpander();
}
}
uint8_t readIOexpander(){
GPIOR1 = 0;
INT_0_OFF; // macro to disable the INT0
i2c_start_wait(addr+I2C_WRITE); // set device address and write mode
i2c_write(reg);
i2c_start(addr+I2C_READ); // restart
GPIOR1 = i2c_readNak();
i2c_stop();
INT_0_ON;
return GPIOR1;
}
unsigned char i2c_readNak(void) {
TWCR = (1<<TWINT) | (1<<TWEN); // | (1<<TWIE);
PORTB |= _BV(PB0); // DEBUG LED ON
while(!(TWCR & (1<<TWINT)));
PORTB &= ~_BV(PB0); // DEBUG LED OFF
return TWDR;
}/* i2c_readNak */
ISR(INT0_vect) {
IRQ_1 |= 0x1;
}
mwilson wrote:CAPTCHAS -- yeah. just had a great comment shot down from the blog because I got the captcha wrong on the first pass, and when I re-entered it, wordpress killed me for commenting too frequently. Little logic glitch there.
These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes are described
later in this section.
uhe wrote:These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes are described
later in this section.
Has anyone found a description of theese status bits anywhere?
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